Local engineers have put together an outline for what could one day be a fully-functioning quantum computer processor.

A team at the Australian Research Council Centre of Excellence for Quantum Computation and Communication Technology (CQC2T) has designed 3D silicon chip architecture based on single atom quantum bits, which is compatible with atomic-scale fabrication techniques.

It is a big step forward in the race to develop a scalable quantum computer in silicon – a material well-understood and favoured by the trillion-dollar computing and microelectronics industry.

Researchers at the CQC2T have already demonstrated a unique fabrication strategy for realising atomic-scale devices, and have developed the world’s most efficient quantum bits in silicon using either the electron or nuclear spins of single phosphorus atoms.

Quantum bits – or qubits – are the fundamental data components of quantum computers.

One of the final hurdles to scaling up to an operational quantum computer is the architecture, which requires figuring out how to precisely control multiple qubits in parallel, across an array of many thousands of qubits, and constantly correct for quantum errors in calculations.

The CQC2T collaboration, involving theoretical and experimental researchers from the University of Melbourne and UNSW, has designed such a device.

Using a new silicon architecture, which uses atomic-scale qubits aligned to control lines – which are essentially very narrow wires – inside a 3D design.

“We have demonstrated we can build devices in silicon at the atomic-scale and have been working towards a full-scale architecture where we can perform error correction protocols – providing a practical system that can be scaled up to larger numbers of qubits,” says UNSW Scientia Professor Michelle Simmons, study co-author and Director of the CQC2T.

“The great thing about this work, and architecture, is that it gives us an endpoint. We now know exactly what we need to do in the international race to get there.”

In the team’s conceptual design, they have moved from a one-dimensional array of qubits, positioned along a single line, to a two-dimensional array, positioned on a plane that is far more tolerant to errors. This qubit layer is “sandwiched” in a three-dimensional architecture, between two layers of wires arranged in a grid.

By applying voltages to a sub-set of these wires, multiple qubits can be controlled in parallel, performing a series of operations using far fewer controls. Importantly, with their design, they can perform the 2D surface code error correction protocols in which any computational errors that creep into the calculation can be corrected faster than they occur.

The team has proposed a strategy to build the device, and have also modelled the required voltages applied to the grid wires needed to address individual qubits and make the processor work.

This architecture gives us the dense packing and parallel operation essential for scaling up the size of the quantum processor,” says Scientia Professor Sven Rogge, Head of the UNSW School of Physics.

“Ultimately, the structure is scalable to millions of qubits, required for a full-scale quantum processor.”